Western Digital has commenced pilot production of the company’s 512 Gigabit, three-bits-per-cell (X3), 64-layer 3D NAND (BICS3) chip, with mass production expected in the second half of 2017. The chip was developed with the company’s technology and manufacturing partner Toshiba. Western Digital introduced initial capacities of the world’s first 64-layer 3D NAND technology in July 2016 and the world’s first 48-layer 3D NAND technology in 2015.
“The launch of the industry’s first 512Gb 64-layer 3D NAND chip doubles the density from when we introduced the world’s first 64-layer architecture in July 2016,” said Siva Sivaram, Western Digital.
“This is a great addition to our rapidly-broadening 3D NAND technology portfolio.
It positions us well to continue addressing the increasing demand for storage.”
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